Parallel gauss-seidel on a torus network-on-chip architecture

Mohammad H. Al-Towaiq*, Khaled Day

*المؤلف المقابل لهذا العمل

نتاج البحث: المساهمة في مجلةArticleمراجعة النظراء

1 اقتباس (Scopus)

ملخص

Network-on-chip multicore architectures with a large number of processing elements are becoming a reality with the recent developments in technology. In these modern systems the processing elements are interconnected with regular network-on-chip (NoC) topologies such as meshes and trees. In this paper we propose a parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a torus NoC architecture. The proposed parallel algorithm is O(Nn2/k2) time complexity for solving a system with matrix of order n on a k × k torus NoC architecture with N iterations assuming n and N are large compared to k (i.e. for large linear systems that require a large number of iterations). We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

اللغة الأصليةEnglish
رقم المقال1250001
دوريةJournal of Interconnection Networks
مستوى الصوت13
رقم الإصدار1-2
المعرِّفات الرقمية للأشياء
حالة النشرPublished - 2012

ASJC Scopus subject areas

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