HW/SW FPGA implementation of vector median filter

A. Boudabous*, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

*المؤلف المقابل لهذا العمل

نتاج البحث

1 اقتباس (Scopus)

ملخص

In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

اللغة الأصليةEnglish
عنوان منشور المضيفProceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
الصفحات101-104
عدد الصفحات4
المعرِّفات الرقمية للأشياء
حالة النشرPublished - 2007
الحدث2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 - Bordeaux
المدة: يوليو ٢ ٢٠٠٧يوليو ٥ ٢٠٠٧

سلسلة المنشورات

الاسمProceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007

Other

Other2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
الدولة/الإقليمFrance
المدينةBordeaux
المدة٧/٢/٠٧٧/٥/٠٧

ASJC Scopus subject areas

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