To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.
|الصفحات (من إلى)||1813-1828|
|دورية||Journal of Engineering and Applied Sciences|
|المعرِّفات الرقمية للأشياء|
|حالة النشر||Published - 2018|
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