An efficient cache organization for on-chip multiprocessor networks

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes a challenging issue. This paper focuses on the interconnection design issues of area, power and performance of chip multiprocessors with shared cache memory. It shows that having a shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. This paper proposes an architectural paradigm in an attempt to gain smaller area occupation allowing more space for an additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper modified the typical MESI cache coherence algorithm to be tailored for the suggested architecture. The experimental results show that the developed architecture produces less broadcast operations compared to the typical algorithm.