TY - JOUR
T1 - An analytical comparison of the spidergon and rectangular mesh NoCs
AU - Moadeli, Mahmoud
AU - Shahrabi, Ali
AU - Vanderbauwhede, Wim
AU - Ould-Khaoua, Mohamed
PY - 2009
Y1 - 2009
N2 - Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.
AB - Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.
KW - Network on-chip
KW - Performance model
KW - Rectangular mesh
KW - Spidergon
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U2 - 10.1142/s0219265909002492
DO - 10.1142/s0219265909002492
M3 - Article
AN - SCOPUS:70249111887
SN - 0219-2659
VL - 10
SP - 167
EP - 188
JO - Journal of Interconnection Networks
JF - Journal of Interconnection Networks
IS - 1-2
ER -