TY - GEN
T1 - A scalable bandwidth aware architecture for connected component labeling
AU - Kumar, Vikram Sampath
AU - Irick, Kevin
AU - Maashri, Ahmed Al
AU - Vijaykrishnan, N.
PY - 2010
Y1 - 2010
N2 - Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.
AB - Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.
KW - Connected component labeling
KW - Single-pass
KW - Slice processing
UR - http://www.scopus.com/inward/record.url?scp=77957958536&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77957958536&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2010.89
DO - 10.1109/ISVLSI.2010.89
M3 - Conference contribution
AN - SCOPUS:77957958536
SN - 9780769540764
T3 - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
SP - 116
EP - 121
BT - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
T2 - IEEE Annual Symposium on VLSI, ISVLSI 2010
Y2 - 5 July 2010 through 7 July 2010
ER -