FPGA Based Digital System Design Using Verilog HDL

المشروع: Other project

تفاصيل المشروع

Description

Over the recent years, a lot of research effort has been put into of improving Hardware Description Languages (HDLs). Currently, HDLs have been used to model the hardware designs as an IEEE standard. The latest iteration of Verilog, formally known as IEEE 1800-2005 System-Verilog, introduces many new features. Using HDLs and their simulators, digital designers are capable of partitioning their designs into components that work concurrently and are able to communicate with each other. The needs of HDLs are much more important where the complexities of ICs are beyond predictions and expectations. Integration at Nano-scale further exaggerate the design and test issues of digital system designs which further calls the HDLs to let understand the designers in depth for the system organization, integration, simulation and test. Through this project the investigator wants to create an environment of a research area in the field of Verilog-HDL in Electrical and Computer Engineering (ECE) department of Sultan Qaboos University (SQU), Oman. At ground level in the curriculum of Computer System and Networks the department has introduced a course of Advance Logic Design with effect from Fall 2011. This project plans to go beyond the awareness and to provide a plate form to build an entire hardware system using a relatively simple programming language and Field-Programmable Gate Array (FPGA) devices. Further, the project is also aimed to look into many other issues of the system design like optimization, power reduction and integration of test methodology.

Layman's description

Over the recent years, a lot of research effort has been put into of improving Hardware Description Languages (HDLs). Currently, HDLs have been used to model the hardware designs as an IEEE standard. The latest iteration of Verilog, formally known as IEEE 1800-2005 System-Verilog, introduces many new features. Using HDLs and their simulators, digital designers are capable of partitioning their designs into components that work concurrently and are able to communicate with each other. The needs of HDLs are much more important where the complexities of ICs are beyond predictions and expectations. Integration at Nano-scale further exaggerate the design and test issues of digital system designs which further calls the HDLs to let understand the designers in depth for the system organization, integration, simulation and test. Through this project the investigator wants to create an environment of a research area in the field of Verilog-HDL in Electrical and Computer Engineering (ECE) department of Sultan Qaboos University (SQU), Oman. At ground level in the curriculum of Computer System and Networks the department has introduced a course of Advance Logic Design with effect from Fall 2011. This project plans to go beyond the awareness and to provide a plate form to build an entire hardware system using a relatively simple programming language and Field-Programmable Gate Array (FPGA) devices. Further, the project is also aimed to look into many other issues of the system design like optimization, power reduction and integration of test methodology.
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